This application claims the benefit of Korean Patent Application No. 1999-67845, filed on Dec. 31, 1999, under 35 U.S.C. xc2xa7 119, the entirety of which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a method of manufacturing a thin film transistor, and more particularly, to a method of manufacturing a thin film transistor for use in a liquid crystal display (LCD) device.
2. Description of Related Art
Liquid crystal display (LCD) devices are in wide use as display devices capable of being reduced in weight, size and thickness. Of these, active matrix LCD devices, where thin film transistors (TFTs) and pixel electrodes are arranged in the form of a matrix, have been widely used due to a high resolution and an excellent performance of implementing moving images.
FIG. 1 is a cross-sectional view illustrating a liquid crystal panel of a typical active matrix LCD device. As shown in FIG. 1, the liquid crystal panel 20 includes lower and upper substrates 2 and 4 with a liquid crystal layer 10 interposed therebetween. The lower substrate 2, referred to as an array substrate, is divided into two regions: a region S; and a region P. TFTs are arranged on the region S as switching elements, and pixel electrodes 14 are arranged on the pixel region P. The upper substrate 4 includes a color filter 8 and a common electrode 12. Through the pixel electrode 14 and the common electrode 12, voltages are applied to the liquid crystal layer 10. In order to prevent a leakage of the liquid crystal, edge portions of the two substrate 2 and 4 are sealed by a sealant 6. The TFT receives signals from external drive integrated circuit (IC) to drive the pixel electrode 14.
An inverted staggered type TFT is used for a general LCD device because its simple structure and a high performance. The inverted staggered type TFT is divided into a back channel etch type and an etch stopper type. Hereinafter, the back channel etch type TFT is explained.
FIG. 2 is a cross-section view illustrating the typical back channel etch type TFT. As shown in FIG. 2, a gate electrode 30 is formed on a substrate 1. A gate insulating layer 32 is formed over the whole surface of the substrate 1 while covering the gate electrode 30. An active layer 34 and an ohmic contact layer 36 are sequentially formed on the gate insulating layer 32. Source and drain electrodes 38 and 40 overlap both end portions of the ohmic contact layer 36.
The gate electrode 30 is made of a low resistive material such as aluminum in order to reduce a RC delay. The gate insulating layer 34 is deposited at a low temperature of less than 350 and is made of SiNx or SiO2. The active layer 34 is made of an hydrogenated amorphous silicon (a-Si:H). The ohmic contact layer 36 is formed in such a way that a gas containing a boron (B) of a boron group or a phosphorous (P) of a nitrogen group is ion-doped into the amorphous silicon layer. The ohmic contact layer 36 is generally is made of n+-type hydrogenated amorphous silicon (n+ a-Si:H) doped with PH3 containing a phosphorous (P). The source and drain electrodes 42 and 44 are made of Cr or Mo.
In order to form the TFT, a deposition process is repeated several times, for example, using a plasma-enhanced chemical vapor deposition (PECVD) technique. The gate insulating layer 32, the active layer 34 and the ohmic contact layer 36 undergo a deposition process in the same process chamber.
FIG. 3 is a graph illustrating a relationship between an RF-power used to form a layer and each of the layers 32, 34 and 36 when the gate insulating layer 32, the active layer 34 and the ohmic contact layer 36 are deposited.
In order to form the gate insulating layer 32, a mixed gas of NH3, N2 and SiH4 is injected into the process chamber and is decomposed by plasma, so that a silicon nitride film (SiNx) is formed on the substrate.
In order to form the active layer 34, NH3 and N2 that are used to deposit the gate insulating layer 32 are pumped out, and H2 are added. The pure amorphous silicon (a-Si:H) is formed using SiH4 and H2.
Then, in order to form the ohmic contact layer 36, a small amount of PH3 is added to the mixed gas of SiH4 and H2 to form an n+ type amorphous silicon layer (a-Si:H).
The active layer 34 generally contains a hydrogen (H). Electrical characteristics of the amorphous silicon TFTs depend on a density of state (DOS). The silicon atoms of the active layer 34 have 4 outmost electrons, among them uncombined electrons cause a dangling bond problem. The dangling bond problem can be solved by the hydrogen.
As described above, in order to remove the mixed gases used to deposit the gate insulating layer, the active layer and the ohmic contact layer, plasma condition should be released first. After a predetermined time passes, the mixed gas in the process chamber is pumped.
FIG. 4 is a graph illustrating a relationship between an internal pressure variation of the process chamber and each of the layers when the gate insulating layer 32, the active layer 34 and the ohmic contact layer 36 are deposited. After a deposition of the gate insulating layer 32, since the mixed gas is removed in the state that the plasma condition is released, an internal pressure of the process chamber varies suddenly. When the internal pressure of the process chamber varies, the polymer generated during the deposition process may fall onto a surface of the gate insulating layer, leading to inferiority in subsequent processes.
Further, when the active layer is formed, a predetermined time is required to maintain an initial plasma state. At this time, the deposited active layer has defects suchas a dangling bond. As a result, the quality of an interface between the insulating layer and the active layer becomes inferior, and therefore current-voltage characteristics of the TFT are lowered.
Furthermore, an interface (see a portion xe2x80x9cAxe2x80x9d of FIG. 2) between the gate insulating layer and the active layer may have defects due to a lattice mismatch because of the difference of the atoms of the insulating layer and the active layer when the thin films are formed, thereby deteriorating electrical characteristics of the TFT. In other words, a threshold voltage of the TFT may increase, a switching operation may become impossible, and there may come a problem in stability. For example, charges are accumulated on the interface between the gate insulating layer 32 and the active layer 34, thereby lowering an ON current and deteriorating the operation of the TFT.
To overcome the problems described above, preferred embodiments of the present invention provide a method of manufacturing a thin film transistor minimizing defects generated when thin films of the thin film transistor are formed.
It is another object of the invention to provide a method of forming thin films for the thin film transistor, which can lower the manufacturing time.
In order to achieve the above and other objects, the preferred embodiments of the present invention provide a method of manufacturing a thin film transistor, including: preparing a process chamber having a stage; providing a substrate on the stage of the process chamber; injecting a first mixed gas of NH3, N2 and SiH4 into the process chamber; forming a silicon nitride film (SiNx) on the substrate with the first mixed gas by creating a plasma state in the process chamber; injecting a second mixed gas of H2 and SiH4 into the process chamber while removing the first mixed gas in the plasma state; forming a pure amorphous silicon film (a-Si:H) on the silicon nitride film using the second mixed gas in the plasma state; injecting a third mixed gas of H2, SiH4 and PH3 into the process chamber while removing the second mixed gas in the plasma state; and forming a doped amorphous silicon film (n+ a-Si:H) on the silicon nitride film using the third mixed gas in the plasma state.
The method further includes forming a gate electrode before the step of forming the silicon nitride film; and forming source and drain electrodes on the doped amorphous silicon film. The method further includes performing a hydrogen plasma treatment on a surface of the silicon nitride film before the step of forming the pure amorphous silicon film. The method further includes performing a hydrogen plasma treatment on a surface of the pure amorphous silicon film before the step of forming the doped amorphous silicon film.
The method of manufacturing the TFT according to the preferred embodiment of the present invention has the following advantages. Firstly, since each of the thin films is deposited in the plasma state, variation of an internal atmosphere of the process chamber is minimized, whereupon a processing time is shortened. Secondly, since the thin films deposited are hydrogen plasma-treated, the hydrogen plasma removes defects at the interface between the thin films, whereupon defects can be prevented. Thirdly, since each of the thin films is deposited under the same pressure, an occurrence of a polymer in the process chamber can be prevented, and interface characteristics of the thin films can be improved significantly.